Power-Constrained Testing of VLSI Circuits: A Guide to the IEEE 1149.4 Test Standard (Frontiers in Electronic Testing)
This text focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. It surveys existing techniques and presents several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths.
Specifications of Power-Constrained Testing of VLSI Circuits: A Guide to the IEEE 1149.4 Test Standard (Frontiers in Electronic Testing)
|Author||Nicola Nicolici, Bashir M. Al-Hashimi|
|Number Of Pages||178|
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