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Advanced ASIC Chip Synthesis: Using Synopsys Design Compiler and Primetime,Used
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Advanced ASIC Chip Synthesis: Using Synopsys Design Compiler and PrimeTime describes the advanced concepts and techniques used for ASIC chip synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted for VDSM (VeryDeepSubMicron) technologies is covered in detail.The emphasis of this book is on realtime application of Synopsys tools used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, submicron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and workarounds described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and backend integration (links to layout) are also discussed at length. Furthermore, the book contains indepth discussions on the basics of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solutions.Advanced ASIC Chip Synthesis: Using Synopsys Design Compiler and PrimeTime is intended for anyone who is involved in the ASIC design methodology, starting from RTL synthesis to final tapeout. Target audiences for this book are practicing ASIC design engineers and graduate students undertaking advanced courses in ASIC chip design and DFT techniques.From the Foreword:This book, written by Himanshu Bhatnagar, provides a comprehensive overview of the ASIC design flow targeted for VDSM technologies using the Synopsis suite of tools. It emphasizes the practical issues faced by the semiconductor design engineer in terms of synthesis and the integration of frontend and backend tools. Traditional design methodologies are challenged and unique solutions are offered to help define the next generation of ASIC design flows. The author provides numerous practical examples derived from realworld situations that will prove valuable to practicing ASIC design engineers as well as to students of advanced VLSI courses in ASIC design'.Dr Dwight W. Decker, Chairman and CEO, Conexant Systems, Inc., (Formerly, Rockwell Semiconductor Systems), Newport Beach, CA, USA.
⚠️ WARNING (California Proposition 65):
This product may contain chemicals known to the State of California to cause cancer, birth defects, or other reproductive harm.
For more information, please visit www.P65Warnings.ca.gov.
- Q: What topics does 'Advanced ASIC Chip Synthesis' cover? A: The book covers advanced concepts and techniques used for ASIC chip synthesis, formal verification, and static timing analysis, particularly using the Synopsys suite of tools.
- Q: Who is the target audience for this book? A: The target audience includes practicing ASIC design engineers and graduate students engaged in advanced courses in ASIC chip design and DFT techniques.
- Q: What is the significance of HDL coding styles in this book? A: The book emphasizes HDL coding styles as a crucial aspect of synthesis and optimization, aimed at achieving optimal synthesis solutions for complex ASIC designs.
- Q: Is this book suitable for beginners in ASIC design? A: While the book provides valuable insights, it is primarily intended for those with some background in ASIC design methodology, making it more suitable for intermediate to advanced readers.
- Q: What is the condition of this book? A: The book is listed as 'Used Book in Good Condition', indicating it may have minor signs of use but is still in a readable and usable state.
- Q: How many pages does 'Advanced ASIC Chip Synthesis' have? A: The book contains 284 pages.
- Q: What type of binding does this book have? A: The book is available in hardcover binding, which provides durability and a professional appearance.
- Q: When was 'Advanced ASIC Chip Synthesis' published? A: The book was published on May 31, 1999.
- Q: Who is the author of this book? A: The book is authored by Himanshu Bhatnagar.
- Q: Does the book address issues related to layout in ASIC design? A: Yes, the book discusses crucial layout issues, including clock tree synthesis and back-end integration, which are essential for ASIC design.