Design of CostEfficient Interconnect Processing Units: Spidergon STNoC (SystemonChip Design and Technologies),Used
Design of CostEfficient Interconnect Processing Units: Spidergon STNoC (SystemonChip Design and Technologies),Used

Design of CostEfficient Interconnect Processing Units: Spidergon STNoC (SystemonChip Design and Technologies),Used

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SKU: SONG1420044710
Brand: CRC Press
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Streamlined Design Solutions Specifically for NoCTo solve critical networkonchip (NoC) architecture and design problems related to structure, performance and modularity, engineers generally rely on guidance from the abundance of literature about betterunderstood systemlevel interconnection networks. However, onchip networks present several distinct challenges that require novel and specialized solutions not found in the triedandtrue systemlevel techniques.A Balanced Analysis of NoC ArchitectureAs the first detailed description of the commercial Spidergon STNoC architecture, Design of CostEfficient Interconnect Processing Units: Spidergon STNoC examines the highly regarded, costcutting technology that is set to replace wellknown shared bus architectures, such as STBus, for demanding multiprocessor systemonchip (SoC) applications. Employing a balanced, wellorganized structure, simple teaching methods, numerous illustrations, and easytounderstand examples, the authors explain:how the SoC and NoC technology works why developers designed it the way they did the systemlevel design methodology and tools used to configure the Spidergon STNoC architecture differences in cost structure between NoCs and systemlevel networksFrom professionals in computer sciences, electrical engineering, and other related fields, to semiconductor vendors and investors all readers will appreciate the encyclopedic treatment of background NoC information ranging from CMPs to the basics of interconnection networks. The text introduces innovative systemlevel design methodology and tools for efficient design space exploration and topology selection. It also provides a wealth of key theoretical and practical MPSoC and NoC topics, such as technological deep submicron effects, homogeneous and heterogeneous processor architectures, multicore SoC, interconnect processing units, generic NoC components, and embeddings of common communication patterns.

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