DesignforTest and Test Optimization Techniques for TSVbased 3D Stacked ICs,Used

DesignforTest and Test Optimization Techniques for TSVbased 3D Stacked ICs,Used

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SKU: DADAX3319023772
Brand: Springer
Condition: New
$125.49
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This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize throughsiliconvias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cuttingedge research in this domain. Coverage includes topics ranging from dielevel wrappers, selftest circuits, and TSV probing to testarchitecture design, test scheduling, and optimization. Readers will benefit from an indepth look at testtechnology solutions that are needed to make 3D ICs a reality and commercially viable.

⚠️ WARNING (California Proposition 65):

This product may contain chemicals known to the State of California to cause cancer, birth defects, or other reproductive harm.

For more information, please visit www.P65Warnings.ca.gov.

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