Title
Hardware Architectures for PostQuantum Digital Signature Schemes,Used
Delivery time: 8-12 business days (International)
This book explores Cbased design, implementation, and analysis of postquantum cryptography (PQC) algorithms for signature generation and verification. The authors investigate NIST round 2 PQC algorithms for signature generation and signature verification from a hardware implementation perspective, especially focusing on Cbased design, powerperformanceareasecurity (PPAS) tradeoffs and design flows targeting FPGAs and ASICs.Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including latticebased, codebased, and multivariatebased; Demonstrates the hardware (FPGA and ASIC) and hardwaresoftware optimizations and tradeoffs of the NIST round 2 signaturebased PQC algorithms; Enables designers to build hardware implementations that are resilient to a variety of sidechannels.
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⚠️ WARNING (California Proposition 65):
This product may contain chemicals known to the State of California to cause cancer, birth defects, or other reproductive harm.
For more information, please visit www.P65Warnings.ca.gov.
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We provide a 2-year limited warranty, from the date of purchase for all our products.
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This warranty strictly does not cover damages that arose from negligence, misuse, wear and tear, or not in accordance with product instructions (dropping the product, etc.).
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