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If you have any questions, you are always welcome to contact us. We'll get back to you as soon as possible, withing 24 hours on weekdays.
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Technology scaling has made billion transistors design feasible on a single die. With transistors getting cheaper and faster, the core count in multiprocessor systems has been steadily increasing. High end servers, gigabit Ethernet routers and multimedia processors now serve workloads dealing with terabytes of data flow every second. Even medium throughput applications now prefer multicore architectures over a single core implementation for better energy efficiency and fault tolerance. These system need a network to communicate data among processing and storage elements in the chip. Although processing units are getting smaller and simpler, the dramatic rise of their number in a single die has resulted in the growing complexity of interconnect.Hence, the design paradigm for multicore chips is gradually shifting from a corecentric architecture towards an interconnectcentric architecture, where overall system performance is limited by the bandwidth of the interconnect fabric rather than the processing ability of any individual core. This work is an attempt to analyse the challenges resulting from this paradigm shift and address them with circuit and architectural innovations.
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