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Packet switches are at the heart of modern communication networks. Initially deployed for local and widearea computer networking, they are now being used in different contexts, such as interconnection networks for HighPerformance Computing (HPC), Storage Area Networks (SANs) and SystemsonChip (SoC) communication. Each application domain, however, has peculiar requirements in terms of bandwidth, latency, scalability and delivery guarantee.In this thesis we present two novel switching architectures, aimed at sharedmemory supercomputing and storage networking respectively. We describe the general architecture of the two systems and discuss how specific requirements and current technology trends have impacted the design. More important, we present architectural innovations that address important issues concerning performance and scalability of inputqueued switches.We propose techniques that enable the construction of distributed (multichip) schedulers for large crossbars, develop a scheme for integrated scheduling of unicast and multicast traffic and and study flowcontrol mechanisms that enable lossless behavior while providing finegrained control of active flows.
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