Title
Impact of Leakage Power Reduction Techniques on Parametric Yield: LowPower Design of Digital Integrated Circuits under Process ,Used
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With the advancement of process technology for fabrication of integrated circuits, the magnitude of variations in process parameters have increased and the parametric yield loss problem has become a serious concern of the fabrication houses. Thus, the traditional techniques for power and delay optimization in design automation tools can no longer be used effectively. This has opened up a challenge to the chip designers to design integrated circuits, which are variation tolerant and thereby having higher parametric yield. In this monograph, a single threshold voltage based approach is proposed that exhibits runtime leakage power reduction comparable to the existing dual threshold voltage assignment approaches and at the same time the proposed approach is less sensitive to process parameter variations. Again, this logiclevel runtime leakage reduction technique is combined with multiple supply voltage assignment during highlevel synthesis for total power reduction. It is believed that the proposed leakage power reduction technique will be useful in digital circuit design flow (logiclevel and highlevel syntheses) under process parameter variation.
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