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This book consists of six publications and an overview of the research topic. The research described in this book concentrates on the design of phaselocked loop radio frequency synthesizers for wireless applications. In particular, the focus is on the implementation of the prescaler, the phase detector and the chargepump. This work reviews the requirements set for the frequency synthesizer by the wireless standards, and how these requirements are derived from the system specifications. These requirements apply to both integerN and fractionalN synthesizers. The work also introduces the special considerations related to the design of fractionalN phaselocked loops. Implementation alternatives for the different building blocks of the synthesizer are reviewed, and new topologies for the phase detector and the chargepump as well as improved topologies for high speed CMOS prescalers are introduced. The experimental results show that the presented topologies can be successfully used in both integerN and fractionalN synthesizers with stateoftheart performance. Finally, additional considerations of integrating a frequency synthesizer into a full transceiver chip are discussed
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