IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection (Analog Circuits and Sig,Used

IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection (Analog Circuits and Sig,Used

In Stock
SKU: DADAX3319373587
Brand: Springer
Condition: New
$65.96
Quantity
Add to wishlist
Add to compare
Sold by Ergodebooks, an authorized reseller.

Processing time: 1-3 days

US Orders Ships in: 3-5 days

International Orders Ships in: 8-12 days

Return Policy: 15-days return on defective items

Payment Option
Payment Methods

Help

If you have any questions, you are always welcome to contact us. We'll get back to you as soon as possible, withing 24 hours on weekdays.

Customer service

All questions about your order, return and delivery must be sent to our customer service team by e-mail at yourstore@yourdomain.com

Sale & Press

If you are interested in selling our products, need more information about our brand or wish to make a collaboration, please contact us at press@yourdomain.com

This book describes the life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection. Various tradeoffs in the design process are discussed, including those associated with many of the most common memory cores, controller IPs and systemonchip (SoC) buses. Readers will also benefit from the authors practical coverage of new verification methodologies. such as bug localization, UVM, and scanchain. A SoC case study is presented to compare traditional verification with the new verification methodologies.Discusses the entire life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection;Introduce a deep introduction for Verilog for both implementation and verification point of view.Demonstrates how to use IP in applications such as memory controllers and SoC buses.Describes a new verification methodology called bug localization;Presents a novel scanchain methodology for RTL debugging;Enables readers to employ UVM methodology in straightforward, practical terms.

⚠️ WARNING (California Proposition 65):

This product may contain chemicals known to the State of California to cause cancer, birth defects, or other reproductive harm.

For more information, please visit www.P65Warnings.ca.gov.

Recently Viewed