Layout Minimization of CMOS Cells (The Springer International Series in Engineering and Computer Science, 160),Used

Layout Minimization of CMOS Cells (The Springer International Series in Engineering and Computer Science, 160),Used

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SKU: SONG0792391829
Brand: Springer
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The layout of an integrated circuit (lC) is the process of assigning geometric shape, size and position to the components (transistors and connections) used in its fabrication. Since the number of components in modem ICs is enormous, computer aideddesign (CAD) programs are required to automate the difficult layout process. Prior CAD methods are inexact or limited in scope, and produce layouts whose area, and consequently manufacturing costs, are larger than necessary. This book addresses the problem of minimizing exactly the layout area of an important class of basic IC structures called CMOS cells. First, we precisely define the possible goals in area minimization for such cells, namely width and height minimization, with allowance for areareducing reordering of transistors. We reformulate the layout problem in terms of a graph model and develop new graphtheoretic concepts that completely characterize the fundamental area minimization problems for seriesparallel and nonseriesparallel circuits. These concepts lead to practical algorithms that solve all the basic layout minimization problems exactly, both for a single cell and for a onedimensional array of such cells. Although a few of these layout problems have been solved or partially solved previously, we present here the first complete solutions to all the problems of interest.

⚠️ WARNING (California Proposition 65):

This product may contain chemicals known to the State of California to cause cancer, birth defects, or other reproductive harm.

For more information, please visit www.P65Warnings.ca.gov.

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