Title
Lowpower 8bit Pipelined ADC with current mode MDAC: (Multiplying DigitaltoAnalog Converter),Used
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In this thesis work we design and optimize a 8bit pipelined ADC for lowpower. The ADC has stage resolution of 1.5bit and employ current mode multiplying digitaltoanalog converter (MDAC). The main focus is to design and optimize the MDAC. We design and optimize the MDAC circuit for the best possible effective number of bits (ENOB), speed and power consumption. Each of the first six stages consisting of SampleandHold, 1.5bit flash ADC and MDAC is realized at the circuit level. The last stage consisting of 2bit flash ADC is also realized at circuit level. The delay logic for synchronization is implemented in VerilogA and MATLAB. A first order digital errorcorrection algorithm is implemented in MATLAB. The design is simulated in UMC 0.18?m technology in Cadence environment.
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