Lowpower Highlevel Synthesis For Nanoscale Cmos Circuits

Lowpower Highlevel Synthesis For Nanoscale Cmos Circuits

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LowPower HighLevel Synthesis for Nanoscale CMOS Circuits addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nanoCMOS technologies. The authors show very largescale integration (VLSI) researchers and engineers how to minimize the different types of power consumption of digital circuits. The material deals primarily with highlevel (architectural or behavioral) energy dissipation because the behavioral level is not as highly abstracted as the system level nor is it as complex as the gate/transistor level. At the behavioral level there is a balanced degree of freedom to explore power reduction mechanisms, the power reduction opportunities are greater, and it can costeffectively help in investigating lower power design alternatives prior to actual circuit layout or silicon implementation.The book is a selfcontained lowpower, highlevel synthesis text for Nanoscale VLSI design engineers and researchers. Each chapter has simple relevant examples for a better grasp of the principles presented. Several algorithms are given to provide a better understanding of the underlying concepts. The initial chapters deal with the basics of highlevel synthesis, power dissipation mechanisms, and power estimation. In subsequent parts of the text, a detailed discussion of methodologies for the reduction of different types of power is presented including: Power Reduction Fundamentals Energy or Average Power Reduction Peak Power Reduction Transient Power Reduction Leakage Power ReductionLowPower HighLevel Synthesis for Nanoscale CMOS Circuits provides a valuable resource for the design of lowpower CMOS circuits.

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