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Adopting new fabrication technologies not only provides higher integration and enhances performance, but also increases the types of manufacturing defects. With design size in millions of gates and working frequency in GHz timingrelated defects havv become a high proportion of the total chip defects. For nanometer technology designs, the stuckat fault test alone cannot ensure a high quality level of chips. Atspeed tests using the transition fault model has become a requirement in technologies below 180nm.Traditional atspeed test methods cannot guarantee high quality test results as they face many new challenges. Supply noise (including IRdrop, ground bounce, and Ldi/dt) effects on chip performance, high test pattern volume, low fault/defect coverage, small delay defect test pattern generation, high cost of test implementation and application, and utilizing lowcost testers are among these challenges. This book discusses these challenges in detail and proposes new techniques and methodologies to improve the overall quality of the transition fault test.
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