Test Resource Partitioning for SystemonaChip (Frontiers in Electronic Testing, 20),Used

Test Resource Partitioning for SystemonaChip (Frontiers in Electronic Testing, 20),Used

Out of Stock
SKU: SONG1461354005
Brand: Springer
$119.99 $171.41
Sold out Save $51.42
Quantity
Add to wishlist
Add to compare

Processing time: 1-3 days

US Orders Ships in: 3-5 days

International Orders Ships in: 8-12 days

Return Policy: 15-days return on defective items

Payment Option
Payment Methods

Help

If you have any questions, you are always welcome to contact us. We'll get back to you as soon as possible, withing 24 hours on weekdays.

Customer service

All questions about your order, return and delivery must be sent to our customer service team by e-mail at yourstore@yourdomain.com

Sale & Press

If you are interested in selling our products, need more information about our brand or wish to make a collaboration, please contact us at press@yourdomain.com

Test Resource Partitioning for SystemonaChip is about test resource partitioning and optimization techniques for plugandplay systemonachip (SOC) test automation. Plugandplay refers to the paradigm in which coretocore interfaces as well as coretoSOC logic interfaces are standardized, such that cores can be easily plugged into 'virtual sockets' on the SOC design, and core tests can be plugged into the SOC during test without substantial effort on the part of the system integrator. The goal of the book is to position test resource partitioning in the context of SOC test automation, as well as to generate interest and motivate research on this important topic.SOC integrated circuits composed of embedded cores are now commonplace. Nevertheless, There remain several roadblocks to rapid and efficient system integration. Test development is seen as a major bottleneck in SOC design, and test challenges are a major contributor to the widening gap between design capability and manufacturing capacity. Testing SOCs is especially challenging in the absence of standardized test structures, test automation tools, and test protocols.Test Resource Partitioning for SystemonaChip responds to a pressing need for a structured methodology for SOC test automation. It presents new techniques for the partitioning and optimization of the three major SOC test resources: test hardware, testing time and test data volume.Test Resource Partitioning for SystemonaChip paves the way for a powerful integrated framework to automate the test flow for a large number of cores in an SOC in a plugandplay fashion. The framework presented allows the system integrator to reduce test cost and meet short timetomarket requirements.

⚠️ WARNING (California Proposition 65):

This product may contain chemicals known to the State of California to cause cancer, birth defects, or other reproductive harm.

For more information, please visit www.P65Warnings.ca.gov.

Recently Viewed