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The Verilog Hardware Description Language (VerilogHDL) has long been the most popular language for describing complex digital hardware. It started life as a prop etary language but was donated by Cadence Design Systems to the design community to serve as the basis of an open standard. That standard was formalized in 1995 by the IEEE in standard 13641995. About that same time a group named Analog Verilog International formed with the intent of proposing extensions to Verilog to support analog and mixedsignal simulation. The first fruits of the labor of that group became available in 1996 when the language definition of VerilogA was released. VerilogA was not intended to work directly with VerilogHDL. Rather it was a language with Similar syntax and related semantics that was intended to model analog systems and be compatible with SPICEclass circuit simulation engines. The first implementation of VerilogA soon followed: a version from Cadence that ran on their Spectre circuit simulator. As more implementations of VerilogA became available, the group defining the a log and mixedsignal extensions to Verilog continued their work, releasing the defi tion of VerilogAMS in 2000. VerilogAMS combines both VerilogHDL and VerilogA, and adds additional mixedsignal constructs, providing a hardware description language suitable for analog, digital, and mixedsignal systems. Again, Cadence was first to release an implementation of this new language, in a product named AMS Designer that combines their Verilog and Spectre simulation engines.
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