Title
The Microarchitecture of Pipelined and Superscalar Computers,Used
Sold by Ergodebooks, an authorized reseller.
Returns accepted within 30 days | support@ergodebooks.com
Shipping Information
- Free Standard Shipping — United States only
- Processing Time: 1–3 business days
- Estimated Delivery: 3–5 business days after dispatch
- Double-boxed, fully insured & discreetly packaged
- Tracking number sent via email once dispatched
- Orders over $250 require signature upon delivery. Taxes calculated at checkout.
Returns & Refund
Returns accepted within 30 days of delivery.
Damaged or Defective Item
Free return shipping + replacement or full refund
Wrong Item Received
Free return shipping + replacement or full refund
Change of Mind
Return shipping at customer's expense · 25% restocking fee applies
Payment Option
This book is intended to serve as a textbook for a second course in the im plementation (Le. microarchitecture) of computer architectures. The subject matter covered is the collection of techniques that are used to achieve the highest performance in singleprocessor machines; these techniques center the exploitation of lowlevel parallelism (temporal and spatial) in the processing of machine instructions. The target audience consists students in the final year of an undergraduate program or in the first year of a postgraduate program in computer science, computer engineering, or electrical engineering; professional computer designers will also also find the book useful as an introduction to the topics covered. Typically, the author has used the material presented here as the basis of a fullsemester undergraduate course or a halfsemester post graduate course, with the other half of the latter devoted to multipleprocessor machines. The background assumed of the reader is a good first course in computer architecture and implementation to the level in, say, Computer Organization and Design, by D. Patterson and H. Hennessy and familiarity with digitallogic design. The book consists of eight chapters: The first chapter is an introduction to all of the main ideas that the following chapters cover in detail: the topics covered are the main forms of pipelining used in highperformance uniprocessors, a taxonomy of the space of pipelined processors, and performance issues. It is also intended that this chapter should be readable as a brief "standalone" survey.
⚠️ WARNING (California Proposition 65):
This product may contain chemicals known to the State of California to cause cancer, birth defects, or other reproductive harm.
For more information, please visit www.P65Warnings.ca.gov.