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In this book, detailed investigation of a recently proposed transistorlevel defecttolerant technique for nanoelectronics is performed. The investigated technique replaces each transistor by an N^2transistor structure (N=2,3,k) and guarantees defect tolerance of all permanent defects of multiplicity = (N1) in each transistor structure. The theoretical and experimental analysis for the defect tolerance of stuckopen and stuckshort defects for quadded transistor structure i.e.,(N=2) is extended for the nona transistor structure i.e.,(N=3). Comparison of defect tolerance of transistor structures (N=2,3) against other techniques like Triple Intervowen Redundancy (TIR) and Quadded Logic (QL) is carried out experimentally. It is shown that the combinations of defect tolerance at both the transistor level and gate level have significantly improved circuit defect tolerance. For this, combination of Triple Modular Redundancy (TMR) with majority gate implemented with N^2transistor structure is investigated in this thesis. Application of N^2transistor structure for handling soft errors is also investigated and a novel approach based on quadded transistor structure is proposed.
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