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Advances in VLSI technology have enabled its deployment into complex circuits. Synthesis flow of such circuits comprises various phases where each phase performs the task algorithmically providing for ingenious interventions of experts. The gap between the original behaviour and the finally synthesized circuit is too wide to be analyzed by any reasoning mechanism. The validation tasks, therefore, must be planned to go handinhand with each phase of synthesis with scope to handle the special characteristics of each synthesis subtask separately. This book is concerned with handinhand verification and (highlevel) synthesis of digital circuits. The verification problem is formulated as equivalence checking between two finite state machines with datapaths (FSMD). The difficulties of each phase are identified and the verification methods based on equivalence of two FSMDs have been formulated accordingly. A highlevel synthesis tool, called structured architecture synthesis tool (SAST), has been developed which support handinhand synthesis and verification.
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