Verilog Styles for Synthesis of Digital Systems,Used

Verilog Styles for Synthesis of Digital Systems,Used

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SKU: SONG0201618605
Brand: Pearson
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This book is designed specifically to make the cuttingedge techniques of digital hardware design more accessible to those just entering the field. The text uses a simpler language (Verilog) and standardizes the methodology to the point where even novices can get medium complex designs through to gatelevel simulation in a short period of time. Requires a working knowledge of computer organization, Unix, and X windows. Some knowledge of a programming language such as C or Java is desirable, but not necessary. Features a large number of worked examples and problemsfrom 100 to 100k gate equivalentsall synthesized and successfully verified by simulation at gate level using the VCS compiled simulator, the FPGA Compiler and Behavioral Compiler available from Synopsys, and the FPGA tool suites from Altera and Xilinx. Basic Language Constructs. Structural and Behavioral Specification. Simulation. Procedural Specification. Design Approaches for Single Modules. Validation of Single Modules. Finite State Machine Styles. ControlPoint Writing Style. Managing ComplexityLarge Designs. Improving Timing, Area, and Power. Design Compiler. Synthesis to Standard Cells. Synthesis to FPGA. Gate Level Simulation and Testing. Alternative Writing Styles. Mixed Technology Design. For anyone wanting an accessible, accelerated introduction to the cuttingedge tools for Digital Hardware Design.

⚠️ WARNING (California Proposition 65):

This product may contain chemicals known to the State of California to cause cancer, birth defects, or other reproductive harm.

For more information, please visit www.P65Warnings.ca.gov.

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