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VLSI Fault Modeling and Testing Techniques: (VLSI Design Automation Series),Used
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VLSI systems are becoming very complex and difficult to test. Traditional stuckat fault problems may be inadequate to model possible manufacturing defects in the integrated ciruit. Hierarchial models are needed that are easy to use at the transistor and functional levels. Stuckopen faults present severe testing problems in CMOS circuits, to overcome testing problems testable designs are utilized. Bridging faults are important due to the shrinking geometry of ICs. BIST PLA schemes have common featurescontrollability and observability which are enhanced through additional logic and test points. Certain circuit topologies are more easily testable than others. The amount of reconvergent fanout is a critical factor in determining realistic measures for determining test generation difficulty. Test implementation is usually left until after the VLSI data path has been synthesized into a structural description. This leads to investigation methodologies for performing design synthesis with test incorporation. These topics and more are discussed.
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