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The performance of the deep submicron technology CMOS integrated circuits is limited by the wired chiptochip and onchip interconnects. This work proposes two technologies for widening up this bottleneck. For the onchip buses we propose the introduction of spatial and temporal coding techniques, which provide substantial increase of the data rate at the price of a simple coding hardware. The chiptochip interconnects can be implemented using wireless data transmission. The areaefficient onchip antenna integration and the achievable chiptochip channel capacities are presented.
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